The present invention relates to a semiconductor integrated circuit routing method and a recording medium which stores routing software.
To perform automatic place & routing using elements such as a standard cell in a semiconductor integrated circuit, it is necessary to place a plurality of elements and then connect the terminals of the elements by wiring lines.
A conventional routing process uses only rectangle information on the outer shapes of the terminal and wiring line. A notch may be formed in connecting a wiring line to an element. As micropatterning in the process progresses, the presence of a circuit pattern containing a notch poses a problem in a patterning process.
If, however, the wiring shape is so changed as to bury the notch, the wiring width becomes larger, and the wiring interval must be widened, undesirably increasing the circuit area.
In some cases, the interval must be designed larger than a wiring interval permitted by the design rule depending on the longitudinal directions of a terminal and wiring line, a wiring enable region where connection of a wiring line to a terminal is enabled, or a wiring disable region where connection of a wiring line is disabled. The conventional routing process is, however, performed on the basis of simple rectangle information of a terminal, as described above. The process cannot be done in consideration of the directions of a terminal and wiring line and the wiring enable region and wiring disable region of a terminal, decreasing the process efficiency or unnecessarily increasing the circuit area.
A reference concerning a conventional routing method is as follows.
Japanese Patent Laid-Open No. 2002-313921